Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane

ABSTRACT

The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

FIELD OF THE INVENTION

The present invention relates to integrated circuits and moreparticularly to semiconductor memory devices of the electricallyerasable and programmable, non-volatile type having a single layer ofgate material.

BACKGROUND OF THE INVENTION

The structure of a conventional memory cell is disclosed, for example,in U.S. Pat. No. 5,761,121 directed to a memory cell for a PMOSstructure. More specifically, such a cell includes a floating-gatetransistor and a control gate which is produced by implantation within asemiconductor substrate. This buried layer, which acts as control gateis capacitively coupled to the floating gate. The control gate and thefloating-gate transistor are electrically isolated by an isolation zone,for example of the STI (Shallow Trench Isolation) type. The layer ofgate material, generally made of polysilicon, within which the floatinggate of the transistor is produced, is isolated from the active zone bya dielectric, for example, silicon dioxide.

Although such a memory cell is programmed by injecting hot electronsinto the floating gate of the transistor, these being called CHE(Channel Hot Electrons), such a memory cell is electrically erased byapplying a high voltage to the source, the drain and the substrate ofthe transistor and by applying a much lower voltage to the control gate.This induces a high reverse electric field and therefore causes theelectrons stored in the floating gate to be extracted and sent into thesource, drain and channel regions of the transistor, and by doing sopassing through the gate oxide of the transistor.

However, this erase process, when it is repeated in a cyclic fashion, asis generally the case for memory applications, causes the gate oxide ofthe transistor and the threshold voltage of this transistor to bedegraded. In other words, repeatedly extracting the electrons throughthe gate oxide of the transistor eventually causes aging of thetransistor. This problem needs to be addressed.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a memory cellstructure that avoids the phenomenon of transistor aging during repeatederase cycles.

It is also an object of the invention to allow the cell to be programmedeither by “hot carrier” programming or by “Fowler-Nordheim” programming.

It is also an object of the invention to provide such a memory cellwhose fabrication process is compatible with a conventional CMOSfabrication process.

The invention therefore provides a semiconductor memory devicecomprising an electrically erasable programmable non-volatile memorycell having a single layer of gate material and including afloating-gate transistor and a control gate. According to a generalfeature of the invention, the source, drain and channel regions of thefloating-gate transistor form the control gate. Moreover, the memorycell includes a dielectric zone lying between a first part of the layerof gate material and a first semiconductor active zone electricallyisolated from a second active zone incorporating the control gate. Thisdielectric zone then forms a “tunnel” zone for transferring, duringerasure of the cell, the charges stored in the floating gate to the saidfirst active zone.

The channel region is understood to mean here as being the semiconductorregion extending between the source region and the drain region beneaththe gate of the transistor.

According to the invention, the structure of the memory cell isconsequently completely different from the conventional structures inthe sense that it has no control gate separate from the floating-gatetransistor. This is because, according to the invention, it is a part ofthe floating-gate transistor, and more particularly the source, drainand channel regions of this transistor, that form the control gate.Moreover, during erasure of the cell, the charges are extracted nolonger through the gate oxide of the floating-gate transistor butthrough a gate oxide (dielectric) which is located opposite an activezone electrically isolated from the active zone incorporating thecontrol gate, and consequently the source, channel and drain regions ofthe floating-gate transistor. As a consequence, according to theinvention, degradation of the oxide in the tunnel zone does not causethe transistor of the cell to undergo ageing.

The fact that the source, drain and channel regions of the transistorform the control gate, and that the tunnel zone located opposite thefirst active zone defines the charge transfer zone, is due to the factthat the capacitive coupling between the second active zone (that inwhich the source, drain and channel regions of the transistor areproduced) and the floating gate is greater than the capacitive couplingwithin the tunnel zone. The differences in capacitive coupling depend onthe areas of gate material opposite the active zones and on thedifferent voltages applied to the various electrodes of the memory cell.A person skilled in the art will know how to adjust these variousparameters to obtain the desired effect.

However, to obtain the advantages of the memory cell according to theinvention, while still applying reasonable voltages to the electrodes ofthe memory cell, that is to say voltages from around a few volts toabout ten volts, it will be advantageous to choose the capacitance ofthe tunnel zone to be less than or equal to 30% of the total capacitancebetween the layer of gate material and all of the active zones of thememory cell.

According to one embodiment of the invention, the transistor has anannular gate and the layer of gate material includes, in addition to theannular gate and the first part, a linking part between this first partand the annular gate.

Several possibilities exist for the electrical isolation between thefirst active zone (that into which the charges will be transferredduring erasure) and the second active zone (that in which the transistoris produced). According to a first embodiment, the first active zone andthe second active zone are electrically isolated from each other by PNjunctions intended to be reverse-biased, and on the surface by anisolation region, for example an isolation region of the shallow trenchtype.

In this case, and according to one embodiment, the first active zone isproduced in a first substrate region (for example a well), having afirst type of conductivity, for example, N-type conductivity. The secondactive zone is produced in a second substrate region (for example awell) also having the first type of conductivity. The first substrateregion and the second substrate region are then separated by a thirdsubstrate region (for example another well) having a second type ofconductivity different from the first, for example P-type conductivity.The isolation region extends between the first substrate region and thesecond substrate region and then includes an aperture emerging in acontact zone (for example a P⁺ zone) in the third semiconductor region.

As a variant, the first active zone and the second active zone may beelectrically isolated from each other solely by PN junctions intended tobe reverse-biased. Such an embodiment allows better data retention to beobtained. This is because it has been observed that it is necessary tochoose a dielectric thickness in excess of 60 Å so as to obtain gooddata retention. However, it has been observed that thinning of the gatedielectric occurs at the interface between the isolation zone, forexample of the shallow trench type, and the gate material. This leads toinferior data retention. Consequently, the embodiment providing forthere to be no overlap of the isolation region by the gate materialaddresses this problem.

More specifically, according to one embodiment, the layer of gatematerial extends entirely above the three or four mentioned substrateregions, without overlapping the isolation region. Whatever theembodiment, the first substrate region includes, on the surface, acontact zone having the first type of conductivity, for example anN⁺-type contact zone in an N well.

This being the case, to facilitate erasure it may prove advantageous toprovide, on the surface of the first active zone, in addition to theaforementioned contact, a surface zone having the second type ofconductivity, for example P⁺-type conductivity, and extending around thetunnel zone. Of course, this surface zone is electrically connected tothe contact zone, for example, by siliciding. Thus, a transistor, forexample a PMOS transistor, whose source and drain regions areshort-circuited will be produced with the first part of the gatematerial. This will allow that part of the active zone located beneaththe first part of the gate material to be very conducting.

It would also be possible not to limit the contact locally, but toproduce, on the surface, any highly doped zone having the first type ofconductivity, for example, N⁺-type conductivity. Doing so would probablyresult in perimetric erasure.

According to one embodiment of the invention, the device furthermoreincludes bias means possessing a memory cell programming state, a memorycell read state and a memory cell erase state. In the erase state, thebias means cause Fowler-Nordheim erasing by applying a voltage to thefirst active zone that is much higher than the voltages applied to thesource, drain and substrate regions of the transistor. In this regard,in the erase state, the bias means preferably apply equal voltages tothe source, drain and substrate regions of the transistor.

In the programming state, the bias means may cause hot-carrierprogramming within the transistor. They may also cause Fowler-Nordheimprogramming, by applying preferably equal voltages to the source, drainand substrate regions of the transistor that are much higher than thoseapplied to the first active zone. Moreover, in the read state, it willbe advantageous to choose a drain/source voltage difference limited to 1volt in absolute value. This prevents very slow reprogramming of thememory cell, or else unintentional, parasitic programming of a virginmemory cell.

The floating-gate transistor is preferably a PMOS transistor. However,the invention also applies to an NMOS transistor. The device maycomprise a memory plane made up of several memory cells. The device maythus form a memory of the EEPROM type or of the FLASH type. The subjectof the invention is also an integrated circuit that includes a device asdefined above.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages and features of the invention will become apparent onexamining the detailed description of non-limiting embodiments and theappended drawings in which:

FIG. 1, 1 a, 1 b diagrammatically illustrate a first embodiment of amemory device according to the invention.

FIGS. 2, 2 a, 2 b diagrammatically illustrate a second embodiment of amemory device according to the invention.

FIGS. 3, 3 a, 3 b diagrammatically illustrate a third embodiment of amemory device according to the invention.

FIG. 4 diagrammatically illustrates biases applied to the electrodes ofa memory device according to the invention, depending on the state ofthis device.

FIG. 5 diagrammatically illustrates a fourth embodiment of a memorydevice according to the invention, particularly one intended to beincorporated within a memory plane.

FIG. 6 illustrates one embodiment of such a memory plane.

FIGS. 7 and 8 diagrammatically illustrate biases applied to theelectrodes of the memory device of FIGS. 5 and 6, depending on the stateof these devices.

FIGS. 9 to 11 diagrammatically illustrate a variant of the invention,which provides two-step hot-carrier programming.

FIG. 12 schematically illustrates a fifth embodiment of a memory deviceaccording to the invention, particularly one intended to be incorporatedwithin a memory plane.

FIGS. 13 and 14 illustrate one embodiment of such a memory plane.

FIG. 15 schematically illustrates the bias voltages applied to theelectrodes of the memory device of FIGS. 12 and 13, depending on thestate of these devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, FIG. 1 a (or alternatively 2 a and 3 a) and FIG. 1 b(or alternatively 2 b and 3 b) are sections on the lines A-A and B-B,respectively, of FIG. 1 (or alternatively of FIG. 2 and FIG. 3). InFIGS. 1 a and 1 b, the reference SB denotes a semiconductor substrate,for example made of P⁻-doped silicon, of an integrated circuit. Thissubstrate SB comprises a first substrate region RG1, formed from anN-doped semiconductor well, and a second substrate region RG2, formedfrom another N-doped semiconductor well. The two wells RG1 and RG2 areseparated by a third semiconductor region RG3 formed from a P-dopedwell.

The well RG3 provides the mutual electrical isolation, depthwise, of thetwo wells RG1 and RG2. This electrical isolation is in fact produced byPN junctions that will be reverse-biased. On the surface, the mutualelectrical isolation of the two wells RG1 and RG2 is provided by anisolation region STI (shallow trench isolation). The isolation regionSTI includes an aperture opening into a P⁺-doped contact zone PSBlocated on the surface of the well RG3. This contact PSB will be used tobias the well RG3 and also the subjacent substrate SB. The well RG1forms a first active zone, while the well RG2 forms a second activezone.

Provided above these two active zones is a layer of a gate material, forexample polysilicon, resting via a gate oxide OX, for example silicondioxide, on the surface of the two active zones. The layer of gatematerial, which in its entirety forms a floating gate, includes a firstpart P1 vertically above the first active zone RG1.

The layer of gate material also includes an annular part FG lying abovethe second active zone RG2. This annular part of the gate materialdefines the gate FG of a PMOS transistor, also called a read or chargestorage transistor, whose source S, formed from a P⁺-type implantedregion lies within the well RG2 outside the annular gate and whose drainD, also formed from a P⁺-type implanted region, lies within the cell RG2inside the ring forming the gate FG. The layer of gate material alsoincludes a linking part PL connecting the annular part FG to the firstpart P1.

The geometry of the first part P1 has been chosen so that thecapacitance of the oxide zone OX located beneath this first part P1, thezone also being called the tunnel zone ZTN for reasons that will beexplained in greater detail below, is less than or equal to 30% of thetotal capacitance between the layer of gate material and all of theactive zones of the memory cell, that is to say the sum of thecapacitances formed between the gate material and each of the activezones of the memory cell.

In this way, the source, drain and channel regions, which arecapacitively coupled to the gate FG, will form a control gate for thismemory cell, while the tunnel zone ZTN will form a charge transfer zonefor extracting, during erasure of the memory cell, the charges stored inthe floating gate, transferring them to the first active zone RG1.

Regarding the control gate, it is of course the channel zone whichcontributes mostly to the capacitive coupling with the annular gate FG.This being so, a person skilled in the art knows that the source anddrain regions also extend, by diffusion, under the annular gate FG. Thesource and drain regions therefore also contribute in practice to thiscapacitive coupling. For suitably biasing the first active zone RG1 andfor making contact, this zone includes an N⁺ implanted zone, with thereference PC1. Moreover, in this embodiment, a P⁺-doped surface zone ZSextending around the tunnel zone ZTN is also provided.

A person skilled in the art will have noted that what has thus beenformed with the first part P1 of the layer of gate material is ashort-circuited PMOS transistor, that is to say one whose P⁺-dopedsource and drain regions are electrically connected together. Thissurface zone ZS is electrically connected to the contact zone PC1, forexample by surface siliciding. Regarding the second active zone RG2,this is also provided with an N⁺ implanted region with the reference BK,for contacting and biasing this well RG2, and consequently for biasing asubstrate of the read transistor.

The process for fabricating such a memory cell firstly comprises theproduction in a manner known per se, of the lateral isolation regionsSTI in the P⁻-type substrate SB. The process then continues, in a mannerknown per se, with the implantation of the wells RG1, RG2 and RG3. Afteran oxide layer OX has been produced on the surface of the structure thusobtained, a layer of gate material, for example polysilicon, is thendeposited, which is etched so as to form in this annular gate layer FG,the linking part PL and the first part P1. Next, the various P⁺ and N⁺implanted regions are produced, the layer of gate material then servingespecially as hard mask.

A conventional siliciding operation is then carried out on the source,drain and contact regions PC1, BK, and on the surface zone ZS. Thefabrication process is then completed with conventional contacts on thesource and drain regions, on the region BK and on the contact PC1.

The operation of the memory cell according to the invention will now bedescribed, more particularly with reference to FIG. 4. In this regard,the memory device according to the invention includes a bias circuit ormeans MPL, for example voltage sources associated with a control logic,these bias means possessing a memory cell programming state, a memorycell read state and a memory cell erase state. In each of these statesthe means MPL deliver voltages VS, VD and VBK, to the source S, thedrain D and the substrate BK of the transistor. They also bias thesubstrate RG3 with a voltage VPSB applied to the contact zone PSB andbias the first active zone RG1 with a voltage VZ1 applied to the contactzone PC1.

Another possibility of electrically programming the memory cell includesadopting what is called “hot electron” programming. More specifically,when it is wished to program the memory cell electrically, that is tosay when it is wished to store charges in the floating gate, a voltageof 5 volts supplied to the source of the transistor and a voltage of 0volts is applied to the drain, for example.

The substrate of the transistor is also biased with 5 volts and avoltage, which may vary in practice between 0 and 5 volts, for example,5 volts, is applied to the contact PC1 of the first active zone. Thesubstrate (contact PSB) is also biased with 0 volts. The transistor isthen in the on state (provided that there is a sufficient gate/sourcevoltage for making the transistor start to conduct), thereby saturatingthis transistor and generating a hole current coming from the source.These holes collide with the crystal lattice and form hot holes and hotelectrons. The hot electrons are attracted to the floating gate, thepotential of which drops slightly with respect to that applied to thesource.

Another possible way of programming the memory cell according to theinvention includes carrying out Fowler-Nordheim programming, that is tosay applying a high electric field in order to lower the energy barriersand allow the electrons to flow towards the floating gate. Morespecifically in this case, equal voltages will, for example be appliedto the source, drain and substrate of the transistor, the value of whichis relatively high, for example between 8 and 11 volts, and typically 11volts. At the same time, while the well RG3 is still biased to 0 volts,a voltage of 0 volts is applied to the contact PC1 of the first activezone. In this way, the floating gate is raised to a potentialsubstantially equal to 10 volts, while the first active zone is at 0volts. This therefore creates a strong electric field which will attractthe electrons from the first active zone RG1 to the floating gatethrough the oxide of the tunnel zone ZTN.

The memory cell according to the invention therefore has the advantageof being able to be programmed in two different ways, either byhot-electron programming or by Fowler-Nordheim programming. It will thusbe possible to choose the type of programming according to the envisagedapplications. Hot-electron programming has a higher current consumption,more rapid, however, than Fowler-Nordheim programming, which has a lowerconsumption. It will therefore be preferable to choose Fowler-Nordheimprogramming in mobile telephony applications.

In the read state, the drain/source voltage difference is intentionallylimited to −1 volt so as to avoid very slow reprogramming of the memorycells. Thus, for example, a voltage of 3.3 volts on the source and avoltage of 2.3 volts on the drain will be chosen. The substrate BK willbe biased with 3.3 volts and the control gate (source and drain) may bebiased with a voltage varying between 0 and 3.3 volts. Thus, if duringprogramming a 0 is programmed into the memory cell, that is to say if,in fact, no programming has been carried out, the transistor will be offduring reading.

On the other hand, if in the programming state a “1” (for example) isprogrammed into the memory cell, that is to say if charges are stored inthe floating gate, the transistor will conduct during reading. Thus, bydetecting whether or not there is a current in the read state it ispossible to determine the logic value that has been written orprogrammed into the cell.

To erase the memory cell, a voltage is applied to the first active zonethat is much higher than those applied to the source, drain andsubstrate regions of the transistor. As an indication, a 0 voltage isapplied to the source, the substrate and the drain of the transistor anda voltage of, for example, 11 volts is applied to the contact PC1, thesubstrate RG3 still being biased with 0 volts. This Fowler-Nordheimerasing therefore leads to the application of a very high electricfield, the reverse of that for programming, and consequently causes thecharges stored in the floating gate to be extracted towards the activezone RG1, via the tunnel ZTN, as far as the contact PC1.

There is therefore no degradation of the oxide of the memory cell'stransistor, which corresponds to the zone of highest coupling. Incertain cases, the erasure of a memory cell may result in this cellbeing in an over-erasure state, for example when the erase time is toolong. This over-erasure state is manifested, when the transistor of thecell is a PMOS transistor, by the presence of positive electricalcharges in the floating gate of the transistor. This state isillustrated in FIG. 9 in terms of the voltage threshold VT. In thatfigure, the curve VT1 corresponds to a threshold voltage of a PMOStransistor of a fabrication output cell. Typically, the thresholdvoltage is around −0.6 volts.

When a cell is programmed by hot electrons, electrons are stored in thefloating gate, which shifts the threshold voltage towards positivevalues, for example to a value of around 1.4 volts (curve VT4). Thethreshold voltage shift is then around 2 volts. The purpose of erasingthis programmed cell is to bring the threshold voltage of the transistorsubstantially back to its initial value (curve VT1).

However, in the event of over-erasure, this is manifested by a shift inthe threshold voltage towards negative values (for example curve VT2).In this case, it may prove extremely difficult, if not impossible, toreprogram the cell. This is because if the absolute value of thethreshold voltage of the transistor remains above the absolute value ofthe gate-source voltage difference, the transistor of the cell cannot beturned on, therefore preventing the production of hot electrons.

To remedy this drawback, the biasing means MPL will program a memorycell having undergone an erasure, the transistor of which is a PMOStransistor, by carrying out hot-electron programming of the transistorin two successive steps, so as firstly to compensate for any residualpositive charges present in the floating gate and then to performoptimum programming (FIG. 10).

More precisely, in the first step, the biasing means MPL compensate forany residual positive charges present in the floating gate by applying acompensation voltage VZ1 to the contact PC1 of the first active zone.This voltage VZ1 is, for example, equal to 0 volts, but it could also benegative, for example greater than about −500 mV. However, it isnecessary to ensure that too negative a compensation voltage is notapplied so as not to bring the PN diode formed by the well RG1 and thewell RG3 into forward conduction.

Applying this compensation voltage, for example for 500 microseconds,not only makes it possible to compensate for the negative shift of thethreshold voltage but also to initiate the hot-electron programming.Thus, at the end of this first step, the threshold voltage is shifted tothe right relative to the initial voltage (curve VT3 shifted to theright relative to curve VT1). The optimum programming is then carriedout by applying, for example for 100 microseconds, a voltage VZ1 to thecontact PC1 of 5 volts. The threshold voltage is then again shifted tothe right (curve VT4).

It will therefore have been noted that this variant of the inventionmakes it possible to obviate the drawback associated with over-erasureby employing two-step programming using the contact PC1 that is normallyused for erasure. The invention is not limited to the embodiment thathas just been described, rather it embraces all variants.

Thus, as illustrated in FIGS. 2, 2 a and 2 b, the N⁺-doped contact PC1of the first active zone may extend over the entire surface of thisfirst active zone, except of course beneath the first part P1 of thegate material. In this case, since there is no implantation in thelinking part PL of the gate material, what is then formed, in the gatematerial is a PIN diode, that is to say a diode formed from a P⁺ regionand an N⁺ region separated by a region of intrinsic gate material.However, during erasing, this diode is reverse-biased and may somewhatcounteract the erasing efficiency. This is the reason why, in someapplications, it will be preferred to use the embodiment illustrated inFIGS. 1, 1 a and 1 b.

In another embodiment, the contact PC1 may remain localized, and theremainder of the N-doped active zone RG1. Another conceivable embodimentis that illustrated in FIGS. 3, 3 a and 3 b. It will be seen in thesefigures that there are no isolation zones STI on the surface between thefirst active zone and the second active zone. In this case, isolation isachieved only by reverse-biased PN junctions.

In the example illustrated in these figures, the first active zone is anN⁺-type implanted surface zone. However, the N⁺ contact could belocalized and could also have a P⁺ implantation of the surface zone typesimilar to that illustrated in FIG. 1. This embodiment, in which thelayer of gate material extends entirely above the active zones of thememory cell without overlapping the lateral isolation region, allowsbetter data retention. This is because the phenomenon of oxide thinningat the interface between an isolation zone and the gate material is thusavoided.

However, it will be necessary in this embodiment to use an appropriatemask during the siliciding step so as not to silicide the floating gateor the PN surface functions, and therefore so as not to create a metalshort circuit. Furthermore, the fact of not siliciding the floating gateallows better data retention. Of course, the programming, reading anderasing of the memory cells like those illustrated in FIGS. 2 and 3 aresimilar to those described with reference to FIG. 1.

Finally, although the electrically erasable programmable non-volatilememory cell that has just been described uses a PMOS transistor,construction based on an NMOS transistor is also conceivable. Moreover,several memory cells may be provided so as to form a memory plane whichcan be erasable bit by bit, so as to form a memory of the EEPROM type,or else erasable by bank or by page so as to form a memory of the FLASHtype, however, it will then be necessary to associate an accesstransistor with each memory cell so as to be able to select it. In thisregard, the embodiment of the cell illustrated in FIG. 5 can be used toproduce a memory plane such as that illustrated in FIG. 6, offering anarchitecture of small size with a high cell programming current and goodisolation between the lines of bits.

This is obtained according to the invention, especially by the use of anaccess transistor having a particular shape which will lead to theaccess transistors of the neighbouring cells being brought intocontribution. More specifically, FIG. 5 illustrates a memory cellCEL_(i) which, assumed here to be flanked by two adjacent memory cellsCEL_(i−1) and CEL_(i+1) located in the same column CL_(j) as the saidmemory cell (FIG. 6), includes an access transistor with the referenceTACS_(i). This access transistor TACS_(i) assigned to the memory cellCEL_(i), partially surrounds the floating-gate FG transistor of thememory cell.

More precisely, this access transistor TACS_(i) may be divided intothree elementary access transistors. Thus, a first elementary accesstransistor TACSEL1 _(i) specifically associated with the memory cellCEL_(i). On the other hand, the second elementary access transistorTACSEL2 _(i) and the third elementary access transistor TACSEL3 _(i) arerespectively common to the two access transistors TACS_(i−1) andTACS_(i+1), which are assigned to the two adjacent memory cellsCEL_(i−1) and CEL_(i+1), respectively. The source of the accesstransistor TACS_(i) forms the source of the first elementary accesstransistor TACSEL1 _(i). Moreover, the drain of the first elementaryaccess transistor TACSEL1 _(i) forms part of the source S of thefloating-gate transistor FG of the memory cell.

Referring now more particularly to FIG. 6, which shows the memory planeformed from the cells illustrated in FIG. 5, it may be seen that eachmemory cell column, for example the column CL_(j) includes a layer ofgate material MTL_(j) possessing a principal part PMTL extending in thedirection of the column along and facing all the floating-gatetransistors FG of the cells. The gate GREL1 _(i) of the first elementarytransistor TACSEL1 _(i) of the access transistor TACS_(i) then includesthat portion of the said principal part of the layer of gate materialMTL_(j) which is located opposite the floating-gate transistor FG of thecell CEL_(i).

Moreover, this layer of gate material MTL_(j) includes, at each memorycell, for example at the memory cell CEL_(i), a second elementaryportion E2MTL_(j) connected to the principal part PMTL_(j) and extendingapproximately perpendicular to this principal part on one side of thefloating-gate transistor. This second elementary portion E2MTL_(j) thenforms part of the gate GREL2 _(i) of the second elementary transistorTACSEL2 _(i).

The layer of gate material MTL_(j) also includes a third elementaryportion E3NMTL_(j), which is also connected to the principal partPMTL_(j) and extends approximately perpendicular to this principal parton the other side of the floating-gate transistor of the cell CEL_(i).This third elementary portion E3MTL_(j) forms part of the gate GREL3_(i) of the third elementary transistor TACSEL3 _(i).

FIG. 6 also shows that the second elementary portion E2MTL_(j)associated with a memory cell forms the third elementary portionassociated with one of the two adjacent memory cells, while the thirdelementary portion E3MTL_(j) associated with the memory cell CEL_(i)forms the second elementary portion associated with the other of theadjacent memory cells. The source of each access transistor TACS_(i)includes a plurality of contacts SLC which are all connected together bymeans of the same metallization.

So as to further increase the current of the access transistor when thelatter is on, other contacts SLC are placed externally near the ends ofthe gates GREL2 _(i) and GREL3 _(i) of the other two elementary accesstransistors. Moreover, the drain contacts BLC of the memory cells of anyone line are connected together and consequently form a bit line. Thelayer of gate material MTL_(j) of each column is also intended to bebiased by a gate bias voltage, and the metallization for taking the gatebias voltage on to the layer MTL_(j) forms a column metallization (rowline). It should therefore be pointed out here that there is no specificcontact on the source S of the floating-gate transistor of a memorycell. This source is consequently floating.

The operation of the memory plane will now be described moreparticularly, also with reference to FIGS. 7 and 8. In general, thememory device according to the invention includes bias means MPL2capable of selecting at least one memory cell in programming mode and inread mode and capable of erasing the memory plane by blocks of cells, inthis case here by two columns simultaneously. This is because it may beseen in FIG. 6 that all the contacts PC1 of the memory cells of twoadjacent columns CL_(j) and CL_(j+1) are connected together by the samemetallization MTL2. On the other hand, in programming or read mode, itwill if necessary be possible to select only a single cell at a time byvarying the bias of the lines of bits and of the column metallizations(row lines).

It is apparent from the architecture illustrated in FIG. 6 that the biasmeans are consequently capable of applying the same source bias voltageto the respective sources SLC of the access transistors assigned to thememory cells of the same column, respectively. Moreover, these biasmeans MPL2 may apply the same gate bias voltage to the respective gatesof the access transistors assigned to the memory cells of any one columnrespectively. Finally, as indicated above, the bias means may apply thesame erase voltage to the respective first active zones RG1 of thememory cells of at least any one column, and in this case in particularof two adjacent columns.

In a manner similar to what has been described in the case of theembodiments illustrated in FIGS. 1 to 3, the bias means MPL2 possess aprogramming state in which they are capable of programming a memorycell. They also possess a read state in which they are capable ofreading a memory cell. Furthermore, they possess an erase state in whichthey are capable of erasing at least one column of memory cells. In eachof these states, the bias means are capable of applying predeterminedvoltages to the sources and the gates of the access transistors, and tothe drains and the substrates of the floating-gate transistors of thecells, and to the first active zones RG1.

We now consider the case in which it is desired to access the cellCEL_(ij), this cell belonging to the line i and to the column j (FIG.7). In general, to access a memory cell in read mode or programmingmode, the bias means MPL2 turn on the access transistors of the memorycells belonging to the same column as that of the memory cell inquestion. Moreover, the bias means apply an identical voltage to thesource of the access transistor and the drain of the floating-gatetransistor of each memory cell of the said column, different from thememory cell in question, so that the other memory cells of the columnare not affected. Finally, the bias means MPL2 can turn off the accesstransistors of the memory cells belonging to a column other than that ofthe memory cell in question.

As an example, as illustrated in FIG. 7, in order to program the cellCEL_(ij) the bias means MPL2 apply, for example, a voltage VMTL=1.7volts to the layer of gate material MTL_(j) of the column CL_(j).Moreover, they apply a voltage VLC, equal to 5 volts, for example, toall the source contacts SLC. Consequently, the gate/source voltagedifference of all the access transistors of all the cells of the columnCL_(j) is equal to −3.3 volts, which consequently turns on all theseaccess transistors. The bias means MPL2 then apply a voltage VBL equalto 0 volts to the contact BLC (bit line) and they apply voltages VBK,VPSB and VZ1, equal to 5 volts, 0 volts and 5 volts respectively, to thecontacts BK, PSB and PC1, respectively.

The cell is then programmed by hot electrons. In this regard, it shouldbe noted here, that the invention is noteworthy in the sense that, sincethe layer of gate material MTL_(j) forms an equipotential, all theaccess transistors, that is to say all the elementary accesstransistors, are on and contribute to delivering the programming currentto the cell in question. Of course, the predominant contribution isprovided by the access transistor of the cell and the contribution of anaccess transistor is smaller the further away this access transistor isfrom the memory cell to which access is made.

Of course, since it is desirable to access only a single cell of thiscolumn and since all the access transistors of the cells of this columnare on, it is then necessary, so as not to affect the other cellsCEL_(mj) (m different from i) of the same column, to apply equalvoltages to the contacts BLC and SLC of these memory cells. In otherwords, since in the present case the voltage VSLC is fixed at 5 volts, avoltage of 5 volts will be applied to the drains (bit line) of the othercells of the column.

Regarding the cells CEL_(mn) (n different from j), that is to say thecells belonging to the columns other than the column that includes thecell to which access is made, the bias means MPL2 apply a voltage VMTLequal to the voltage VSLC to the gates of the access transistorsMTL_(n). Thus, all the access transistors of the cells of these othercolumns are off, since the gate/source voltage difference is zero. Itshould be noted here that very good isolation between two neighbouringbit lines is achieved.

If it is now desired to access the cell CEL_(ij) in read mode, the biasmeans MPL2 apply a voltage equal to 0 volts to the gates of the accesstransistors and a voltage equal to 3.3 volts to the sources of theaccess transistors, so as to turn on the access transistors of the cellsof the columns. In this read state, the drain/source voltage differenceof the floating-gate transistor is intentionally limited to −1 volt soas to avoid very slow reprogramming of the memory cell. A voltage on thedrain of 2.3 volts will then be chosen. The substrate BK will be biasedwith 3.3 volts. In addition, for example, the contact PSB will beearthed and 3.3 volts applied to the contact PC1.

The erasing of the cells of two neighbouring columns is of theFowler-Nordheim type. More specifically, in this erase state, the biasmeans cause Fowler-Nordheim erasing by applying a voltage to the firstactive zones RG1 which is much higher than that applied to the sourceregions of the access transistors and to the drain and substrate regionsof the floating-gate transistors.

Thus, as an indication, as illustrated in FIG. 8, the bias means MPL2may apply a voltage VZ1 of 11 volts to the contact PC1, while all theother contacts will be earthed. It should be noted here that the factthat the source of the floating-gate transistor of the memory cell isitself floating is compatible with Fowler-Nordheim erasing via the firstactive zone RG1. This is because the floating source of the transistoris earthed by the memory location itself.

Of course, in the variant illustrated in FIGS. 5 and 6, an isolation ofthe type illustrated in FIGS. 1, 2 and 3 will be used to mutuallyisolate the various active regions RG1, RG2 and RG3 of the memorylocation. Moreover, two-step hot-electron programming of the cells, asdescribed with reference to FIGS. 1, 2, 3, 9 and 10, may also be appliedto the memory plane of FIG. 6. More precisely as illustrated in FIG. 11,the bias means MPL2 would then apply in this case, for programming thecell CEL_(ij), firstly a zero voltage VZ1 to the contact PC1 via themetallization MTLPC_(i,j+1) (FIG. 6) and an optimum voltage VZ1 of 5volts.

A fifth embodiment of a memory cell according to the invention, allowingthe production of a memory plane requiring less consumption for theprogramming phase, thereby making it particularly advantageous formobile telephone applications for example, will now be described withreference more particularly to FIG. 12 et seq. In FIG. 12, the accesstransistor TACS_(i) assigned to a memory cell CEL_(ij) comprises a gridGRTACS_(i) extending perpendicular to the linking part PL and on theopposite side from this linking part with respect to the annular gateFG.

The source of the access transistor comprises a source contact BL_(j).The drain of the access transistor forms part of the source S of thefloating-gate transistor of the memory cell. The drain of thefloating-gate transistor is electrically connected to the second activezone RG2, that is to say to its substrate (or bulk). The drain zone hasin fact a contact WLP_(i) connected via a metallization (not shown inFIG. 12, but illustrated schematically in FIG. 13), to the bulk contactBK_(i).

As illustrated in FIGS. 13 and 14, all the source contacts of the accesstransistors of the cells of any one column j of the memory plane areconnected together via a column metallization (bit line), in this caseBL_(j). All the first active zones of the cells of any one column j ofthe memory plane are connected together via their PC1 _(j) and viaanother column metallization VER_(j). All the drain contacts, andconsequently all the bulk contacts of the floating-gate transistors ofthe cells of any one line i, are connected together via a linemetallization WLP_(i). The gates GRTACS_(i) of the access transistors ofthe cells of any one line i of the memory plane are connected togetherand the corresponding contacts WL_(i) are also connected together via aline metallization WL_(i). The memory device furthermore includes biasmeans MPL3 (FIG. 15) capable of selecting at least one memory cell inprogramming mode and of programming it by Fowler-Nordheim programming.

More precisely, in this embodiment, the bias means are capable ofselecting a cell of the memory plane and of programming it by applying asufficient potential difference between the drain of the floating-gatetransistor of the cell and the first active zone of this cell. It istherefore not via the access transistor that a cell is selected inprogramming.

An example of the voltages delivered by the bias means MPL3 and appliedto the various metallizations of the memory plane is illustrated in FIG.15 in conjunction with FIG. 13. More precisely, the configuration 1 ofthe table given in the top part of FIG. 15 corresponds to a selectionand programming of the cell CEL₁₁ of FIG. 13. This example assumes thatthe supply voltage VPP of the integrated circuit is equal to 6.6 volts,since the oxide thickness of the transistors of the cells is around 5nanometres. This voltage VPP is applied to the metallizations WL1 andWLP1, while the voltage VPP/2 is applied to the metallizations BL1, BL2,WLP2 and VER2. Finally, the metallizations VER1 and WL2 are earthed.

It therefore follows that the access transistor TACS₁ of the cell CEL₁₁is off and that the potential of the source of the floating-gatetransistor also rises to the voltage VPP by coupling, given that thedrain and the substrate are at this potential. Since there then exists alarge potential difference (typically 5.6 volts) between the floatinggate and the contact PC1 ₁, the cell is programmed by Fowler-Nordheimprogramming.

However, owing to the application of the voltage VPP/2 to themetallization VER2, there is no sufficient potential difference betweenthe drain of the floating-gate transistor of the cell CEL₁₂ and itscontact PC1 ₂, and consequently between the floating gate and thecontact PC1 ₂. The conditions for Fowler-Nordheim programming aretherefore not met. The conditions for Fowler-Nordheim programming arealso not met in the case of the cells CEL₂₁ and CEL₂₂. The bias meansMPL3 are also capable of erasing the memory plane in its entirety, forexample by applying a high voltage to all the first active zones of allthe cells and by applying a zero voltage to the other contacts of thecells.

In this regard, they apply for example, as indicated in theconfiguration 2 of the table in FIG. 15, a zero voltage to themetallizations BL1, WL1, WLP1, BL2, WL2 and WLP2 and the voltage VPP tothe metallizations VER1 and VER2. A Fowler-Nordheim erasing is thereforecarried out. It should be noted here that, as in the variant illustratedin FIGS. 5 and 6, the fact that the source of the floating-gatetransistor of the memory cell is itself floating, is compatible withFowler-Nordheim erasing via the first active zone RG1. This is becausethe floating gate of the transistor is taken to earth via the memorylocation itself. The bias means MPL3 are also capable of reading thememory plane line by line, by turning on the access transistors of thecells of one line and turning off the access transistors of the cells ofthe other lines.

An example of the voltages applied is indicated in the configuration 3of the table in FIG. 15. Throughout all that has just been described inrelation to FIGS. 12 to 15, the bias means MPL3 deliver a zero voltageVPSB to the substrate contact PSB. Of course, in the variant illustratedin FIGS. 12 and 14, it would be possible to use an isolation of the typeof that illustrated in FIGS. 1, 2 and 3 in order to mutually isolate thevarious active regions RG1, RG2 and RG3 of the memory location.

1. A semiconductor memory device comprising: at least one electricallyerasable and programmable non-volatile memory cell including a layer ofgate material, a floating-gate transistor including a floating gatedefined in the layer of gate material, and further including source,drain and channel regions defining a control gate, a first active zone,and a second active zone incorporating the control gate and electricallyisolated from the first active zone, a dielectric zone between a firstpart of the layer of gate material and the first active zone; thedielectric zone defining a transfer zone for transferring, duringerasure of the memory cell, charges stored in the floating gate to thefirst active zone.
 2. The device according to claim 1, wherein thecapacitance of the transfer zone is less than or equal to 30% of a totalcapacitance between the layer of gate material and the active zones ofthe memory cell.
 3. The device according to claim 1, wherein thefloating-gate comprises an annular gate defined in the layer of gatematerial, and wherein the layer of gate material includes a linking partbetween the first part and the annular gate.
 4. The device according toclaim 1, wherein the first active zone and the second active zone areelectrically isolated from each other by reverse-biased PN junctions. 5.The device according to claim 4, wherein the first active zone and thesecond active zone are electrically isolated from each other on asurface of the memory cell by an isolation region.
 6. The deviceaccording to claim 5, wherein the first active zone is disposed in afirst substrate region having a first type of conductivity, the secondactive zone is disposed in a second substrate region having the firsttype of conductivity, the first substrate region and the secondsubstrate region are separated by a third substrate region having asecond type of conductivity, different from the first, and wherein theisolation region extends between the first substrate region and thesecond substrate region and includes an aperture in a contact zone inthe third semiconductor region.
 7. The device according to claim 6,wherein the first substrate region includes, on the surface, a contactzone having the first type of conductivity.
 8. The device according toclaim 4, wherein the first active zone is disposed in a first substrateregion having a first type of conductivity, the second active zone isdisposed in a second substrate region having the first type ofconductivity, the first substrate region and the second substrate regionare separated by a third substrate region having a second type ofconductivity, different from the first, and wherein the layer of gatematerial extends above the three substrate regions without overlappingthe isolation region.
 9. The device according to claim 8, wherein thefirst substrate region includes, on the surface, a contact zone havingthe first type of conductivity.
 10. The device according to claim 9,wherein the first substrate region further includes a surface zonehaving the second type of conductivity and extending around the transferzone, the surface zone being electrically connected to the contact zone.11. The device according to claim 1, wherein the floating gatetransistor comprises a PMOS transistor.
 12. The device according toclaim 1, wherein the at least one memory cell comprises a plurality ofmemory cells defining a memory plane, each memory cell including anaccess transistor.
 13. The device according to claim 1 furthercomprising a bias device possessing a memory cell programming state, amemory cell read state and a memory cell erase state, wherein the biasdevice is for applying, in each of the states, predetermined voltages tothe source, the drain and the substrate of the floating gate transistorand to the first active zone, and wherein, in the erase state, the biasdevice causes Fowler-Nordheim erasing by applying a voltage to the firstactive zone much higher than voltages applied to the source, drain andsubstrate regions of the floating gate transistor.
 14. The deviceaccording to claim 13, wherein in the erase state, the bias deviceapplies equal voltages to the source, drain and substrate regions of thefloating gate transistor.
 15. The device according to claim 13, whereinin the programming state, the bias device causes hot-carrier programmingwithin the floating gate.
 16. The device according to claim 13 wherein,in the programming state, the bias device causes Fowler-Nordheimprogramming by applying equal voltages to the source, drain andsubstrate regions of the floating gate transistor that are much higherthan voltages applied to the first active zone.
 17. The device accordingto claim 13, wherein, in the read state, the drain/source voltagedifference is limited to about 1 volt.
 18. The device according to claim1, wherein the at least one memory cell comprises a plurality of memorycells defining a memory plane, each memory cell including an accesstransistor; wherein the access transistor of a memory cell flanked bytwo adjacent memory cells located in a same column as the memory cellincludes a first elementary access transistor specifically associatedwith the memory cell and second and third elementary access transistorsrespectively common to two access transistors assigned to the twoadjacent memory cells respectively; wherein a source of the accesstransistor forms a source of the first elementary access transistorwhile a drain of the first elementary access transistor forms part ofthe source of the floating-gate transistor of the memory cell; andfurther comprising a bias device for selecting at least one memory cellin program mode and in read mode and for erasing the memory plane viablocks of memory cells.
 19. The device according to claim 18, whereinthe bias device is for applying a same source bias voltage to therespective sources of the access transistors of the memory cells of anyone column respectively, a same gate bias voltage to the respectivegates of the access transistors of the memory cells of the same columnrespectively and the same erase voltage to the respective first activezones of the memory cells of at least the same column.
 20. The deviceaccording to claim 18, wherein the access transistor of a memory cellpartially surrounds the floating gate transistor of the memory cell. 21.The device according to claim 20, wherein each column of memory cellshas a layer of gate material including a main part extending in thedirection of the column along and opposite the floating-gate transistorsof the memory cells; wherein the gate of the first elementary accesstransistor of an access transistor of a memory cell includes a portionof the main part of the layer of gate material which is located oppositethe floating-gate transistor of the memory cell; wherein the layer ofgate material includes, within each memory cell, a second elementaryportion connected to the main part and extending approximatelyperpendicular to the main part on one side of the floating-gatetransistor of the memory cell, to from part of the gate of the secondelementary transistor of the access transistor, and a third elementaryportion connected to the main part and extending approximatelyperpendicular to the main part on the other side of the floating-gatetransistor of the memory cell, to form part of the gate of the thirdelementary transistor of the access transistor; and wherein the secondelementary portion associated with a memory cell defines the thirdelementary portion associated with one of the two adjacent memory cells,and the third elementary portion associated with the memory cell definesthe second elementary portion associated with the other of the twoadjacent memory cells.
 22. The device according to claim 18, wherein thebias device possesses a programming state to program a memory cell, aread state to read a memory cell and an erase state to erase at leastone column of memory cells; wherein the bias device is for applying, ineach of the states, predetermined voltages to the sources and the gatesof the access transistors, and to the drains and the substrates of thefloating-gate transistors of the memory cells and to the first activezones; and wherein, in the erase state, the bias device causesFowler-Nordheim erasing by applying a voltage to the first active zonesthat is much higher than voltages applied to the source regions of theaccess transistors, and to the drain and substrate regions of thefloating-gate transistors.
 23. The device according to claim 22, whereinto access a memory cell in read mode or in programming mode, the biasdevice turns on the access transistors of the memory cells belonging tothe same column as that of the memory cell, applies an identical voltageto the source of the access transistor and the drain of thefloating-gate transistor of each memory cell of the column differenttrout the memory cell, and turns off the access transistors of thememory cells belonging to a column other than that of the memory cell.24. The device according to claim 23, wherein the bias device programs amemory cell that has undergone erasure, the floating gate transistor ofwhich cell is a PMOS transistor, by carrying out hot-electronprogramming on the transistor in two successive steps to firstlycompensate for any residual positive charges present in the floatinggate transistor and then to carry out optimum programming.
 25. Thedevice according to claim 24, wherein in a first step of the two steps,the bias device compensates for any residual positive charges present inthe floating gate transistor by applying a compensation voltage to thecontact zone of the first active zone.
 26. The device according to claim25, wherein the compensation voltage is less than or equal to 0 voltsand greater than about −500 mV.
 27. The device according to claim 3,wherein the at least one memory cell comprises a plurality of memorycells defining a memory plane, each memory cell including an accesstransistor; wherein the access transistor of a memory cell comprises agate extending perpendicular to the linking part and on the oppositeside from the linking part with respect to the annular gate, wherein thesource of the access transistor comprises a source contact, the drain ofthe access transistor forms part of the source of the floating-gatetransistor of the memory cell, and the drain of the floating-gatetransistor is electrically connected to the second active zone.
 28. Thedevice according to claim 27, wherein the source contacts of the accesstransistors of the memory cells of any one column of the memory planeare connected together, the first active zones of the memory cells ofany one column of the memory plane are connected together, the gates ofthe access transistors of the memory cells of any one line of the memoryplane are connected together, and the corresponding gate contacts areconnected together by a line metallization, the drains of thefloating-gate transistors of the memory cells of any one line of thememory plane are connected together to form another line metallization,and further comprising a bias device for selecting at least one memorycell in programming mode and for programming the at least one memorycell by Fowler-Nordheim programming.
 29. The device according to claim28, wherein the bias device selects a memory cell of the memory planeand programs the memory cell by applying a sufficient potentialdifference between the drain of the floating-gate transistor of thememory cell and the first active zone of the memory cell.
 30. The deviceaccording to claim 28, wherein the bias device is for erasing the memoryplane in its entirety.
 31. The device according to claim 30, wherein thebias device erases the memory plane in its entirety by applying a highvoltage to the first active zones of the memory cells and by applying azero voltage to other contacts of the memory cells.
 32. The deviceaccording to one of claim 28, wherein the bias device is for reading thememory plane line by line by turning on the access transistors of thememory cell of a line and by turning off the access transistors of thememory cells of other lines.
 33. The device according to claim 28,wherein the memory plane defines at least one of an EEPROM type memoryand a FLASH type memory.
 34. An integrated circuit comprising asemiconductor memory device according to claim
 31. 35. A method ofmaking a semiconductor memory device comprising: providing at least oneelectrically erasable and programmable non-volatile memory cellincluding a layer of gate material, a floating-gate transistor includinga floating gate defined in the layer of gate material, and furtherincluding source, drain and channel regions defining a control gate, afirst active zone, and a second active zone incorporating the controlgate and electrically isolated from the first active zone, a dielectriczone between a first part of the layer of gate material and the firstactive zone; the dielectric zone defining a transfer zone fortransferring, during erasure of the memory cell, charges stored in thefloating gate to the first active zone.
 36. The method according toclaim 35, wherein the capacitance of the transfer zone is less than orequal to 30% of a total capacitance between the layer of gate materialand the active zones of the memory cell.
 37. The method according toclaim 35, wherein the floating-gate comprises an annular gate defined inthe layer of gate material; and providing the layer of gate materialwith a linking part between the first part and the annular gate.
 38. Themethod according to claim 35, further comprising electrically isolatingthe first active zone and the second active zone from each other byreverse-biased PN junctions.
 39. The method according to claim 38,further comprising electrically isolating the first active zone and thesecond active zone from each other on a surface of the memory cell withan isolation region.
 40. The method according to claim 39, wherein thefirst active zone is disposed in a first substrate region having a firsttype of conductivity, the second active zone is disposed in a secondsubstrate region having the first type of conductivity, the firstsubstrate region and the second substrate region are separated by athird substrate region having a second type of conductivity, differentfrom the first, and wherein the isolation region extends between thefirst substrate region and the second substrate region and includes anaperture in a contact zone in the third semiconductor region.
 41. Themethod according to claim 40, further comprising providing a contactzone having the first type of conductivity on the surface of the firstsubstrate region.
 42. The method according to claim 38, wherein thefirst active zone is disposed a first substrate region having a firsttype of conductivity, the second active zone is disposed in a secondsubstrate region having the first type of conductivity, the firstsubstrate region and the second substrate region are separated by athird substrate region having a second type of conductivity, differentfrom the first, and wherein the layer of gate material extends above thethree substrate regions without overlapping the isolation region. 43.The method according to claim 42, further comprising providing a contactzone having the first type of conductivity on the surface of the firstsubstrate region.
 44. The method according to claim 43, furthercomprising providing a surface zone having the second type ofconductivity and extending around the transfer zone in the firstsubstrate region; and electrically connecting the surface zone to thecontact zone.
 45. The method according to claim 35, wherein the floatinggate transistor comprises a PMOS transistor.
 46. The method according toclaim 35, wherein the at least one memory cell comprises a plurality ofmemory cells defining a memory plane; further comprising providing eachmemory cell with an access transistor.
 47. The method according to claim35 further comprising providing a bias device possessing a memory cellprogramming state, a memory cell read state and a memory cell erasestate, wherein the bias device is for applying, in each of the states,predetermined voltages to the source, the drain and the substrate of thefloating gate transistor and to the first active zone, and wherein, inthe erase state, the bias device causes Fowler-Nordheim erasing byapplying a voltage to the first active zone much higher than voltagesapplied to the source, drain and substrate regions of the floating gatetransistor.
 48. The method according to claim 47, wherein in the erasestate, the bias device applies equal voltages to the source, drain andsubstrate regions of the floating gate transistor.
 49. The methodaccording to claim 47, wherein in the programming state, the bias devicecauses hot-carrier programming within the floating gate transistor. 50.The method according to claim 47 wherein, in the programming state, thebias device causes Fowler-Nordheim programming by applying equalvoltages to the source, drain and substrate regions of the floating gatetransistor that are much higher than voltages applied to the firstactive zone.
 51. The method according to claim 47, wherein, in the readstate, the drain/source voltage difference is limited to about 1 volt.52. The method according to claim 35, wherein the at least one memorycell comprises a plurality of memory cells defining a memory plane;further comprising providing each memory cell with an access transistor;wherein the access transistor of a memory cell flanked by two adjacentmemory cells located in a same column as the memory cell includes afirst elementary access transistor specifically associated with thememory cell and second and third elementary access transistorsrespectively common to two access transistors assigned to the twoadjacent memory cells respectively; wherein a source of the accesstransistor forms a source of the first elementary access transistorwhile a drain of the first elementary access transistor forms part ofthe source of the floating-gate transistor of the memory cell; andfurther comprising a bias device for selecting at least one memory cellin program mode and in read mode and for erasing the memory plane viablocks of memory cells.
 53. The method according to claim 52, whereinthe bias device is for applying a same source bias voltage to therespective sources of the access transistors of the memory cells of anyone column respectively, a same gate bias voltage to the respectivegates of the access transistors of the memory cells of the same columnrespectively and the same erase voltage to the respective first activezones of the memory cells of at least the same column.
 54. The methodaccording to claim 52, wherein the access transistor of a memory cellpartially surrounds the floating gate transistor of the memory cell. 55.The method according to claim 54, wherein each column of memory cellshas a layer of gate material including a main part extending in thedirection of the column along and opposite the floating-gate transistorsof the memory cells; wherein the gate of the first elementary accesstransistor of an access transistor of a memory cell includes a portionof the main part of the layer of gate material which is located oppositethe floating-gate transistor of the memory cell; wherein the layer ofgate material includes, within each memory cell, a second elementaryportion connected to the main part and extending approximatelyperpendicular to the main part on one side of the floating-gatetransistor of the memory cell, to form part of the gate of the secondelementary transistor of the access transistor, and a third elementaryportion connected to the main part and extending approximatelyperpendicular to the main part on the other side of the floating-gatetransistor of the memory cell, to form part of the gate of the thirdelementary transistor of the access transistor; and wherein the secondelementary portion associated with a memory cell defines the thirdelementary portion associated with one of the two adjacent memory cells,and the third elementary portion associated with the memory cell definesthe second elementary portion associated with the other of the twoadjacent memory cells.
 56. The method according to claim 52, wherein thebias device possesses a programming state to program a memory cell, aread state to read a memory cell and an erase state to erase at leastone column of memory cells; wherein the bias device is for applying, ineach of the states, predetermined voltages to the sources and the gatesof the access transistors, and to the drains and the substrates of thefloating-gate transistors of the memory cells and to the first activezones; and wherein, in the erase state, the bias device causesFowler-Nordheim erasing by applying a voltage to the first active zonesthat is much higher than voltages applied to the source regions of theaccess transistors, and to the drain and substrate regions of thefloating-gate transistors.
 57. The method according to claim 52, whereinto access a memory cell in read mode or in programming mode, the biasdevice turns on the access transistors of the memory cells belonging tothe same column as that of the memory cell, applies an identical voltageto the source of the access transistor and the drain of thefloating-gate transistor of each memory cell of the column differentfrom the memory cell, and turns off the access transistors of the memorycells belonging to a column other than that of the memory cell.
 58. Themethod according to claim 57, wherein the bias device programs a memorycell that has undergone erasure, the floating gate transistor of whichcell is a PMOS transistor, by carrying out hot-electron programming onthe transistor in two successive steps to firstly compensate for anyresidual positive charges present in the floating gate transistor andthen to carry out optimum programming.
 59. The method according to claim58, wherein in a first step of the two steps, the bias devicecompensates for any residual positive charges present in the floatinggate transistor by applying a compensation voltage to the contact zoneof the first active zone.
 60. The device according to claim 59, whereinthe compensation voltage is less than or equal to 0 volts and greaterthan about −500 mV.
 61. The method according to claim 37, wherein the atleast one memory cell comprises a plurality of memory cells defining amemory plane; further comprising providing each memory cell with anaccess transistor; wherein the access transistor of a memory cellcomprises a gate extending perpendicular to the linking part and on theopposite side from the linking part with respect to the annular gate;wherein the source of the access transistor comprises a source contact,the drain of the access transistor forms part of the source of thefloating-gate transistor of the memory cell, and the drain of thefloating-gate transistor is electrically connected to the second activezone.
 62. The device according to claim 61, wherein the source contactsof the access transistors of the memory cells of any one column of thememory plane are connected together, the first active zones of thememory cells of any one column of the memory plane are connectedtogether, the gates of the access transistor of the memory cells of anyone line of the memory plane are connected together, and thecorresponding gate contacts are connected together by a linemetallization, the drains of the floating-gate transistors of the memorycells of any one line of the memory plane are connected together to formanother line metallization; and further comprising a bias device forselecting at least one memory cell in programming mode and forprogramming the at least one memory cell by Fowler-Nordheim programming.63. The method according to claim 62, wherein the bias device selects amemory cell of the memory plane and programs the memory cell by applyinga sufficient potential difference between the drain of the floating-gatetransistor of the memory cell and the first active zone of the memorycell.
 64. The method according to claim 62, wherein the bias device isfor erasing the memory plane in its entirety.
 65. The method accordingto claim 64, wherein the bias device erases the memory plane in itsentirety by applying a high voltage to the first active zones of thememory cells and by applying a zero voltage to other contacts of thememory cells.
 66. The method according to claim 62, wherein the biasdevice is for reading the memory plane line by line by turning on theaccess transistors of the memory cell of a line and by turning off theaccess transistors of the memory cells of other lines.
 67. The methodaccording to claim 62, wherein the memory plane defines at least one ofan EEPROM type memory and a FLASH type memory.